A programmable logic device (PLD) allows users to build reconfigurable digital circuits. There are numerous types of programmable logic devices, such as field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). These devices are programmed using a hardware programming language, such as VHSIC Hardware Description Language (VHDL) or Verilog, to describe the desired circuitry. Code is then synthesized on a computing device, and necessary connections are placed and routed to generate a bit-map. The bit-map is downloaded to the programmable logic device to create the operative circuitry.
Hardware programming languages are very powerful and can be used to create complex designs. However, the resultant circuitry must be tested for errors or “bugs” which could arise during coding, synthesis, bit-map generation, or implementation on a PLD. Tools are thus needed to correctly diagnose a problem with the circuitry on a PLD by identifying the source of the problem, thereby facilitating development of a solution. Diagnosing the problem typically involves sampling various nodes of the PLD to determine their state at a point in time.
Currently, there are two primary techniques to test PLDs: (1) using an external logic analyzer, and (2) using an on-chip logic analyzer circuit. When an external logic analyzer is used, it is connected to a PLD. This requires the user to alter the bit-map for the PLD such that the desired nodes for sample are mapped to available user input/output (I/O) buffers on the PLD. Using an external logic analyzer is not preferable because external logic analyzers are very expensive. Additionally, free user I/O buffers are not always available.
An on-chip logic analyzer circuit samples various internal nodes of a PLD based on specified trigger conditions and stores the captured signals in on-chip block memories. An embedded logic analyzer circuit for a PLD is described in U.S. Pat. No. 6,182,247. As depicted in FIG. 1, logic analyzer circuit 120 samples at nodes between user logic circuitry 111. Trigger signal 103 of User logic trigger node 102 is sampled by trigger signal circuit 121. When Trigger signal circuit 121 determines a trigger condition is et, capture signal circuit 122 stores capture signal 104 of user logic circuit capture node 101.
While the described on-chip logic analyzer circuit tries to solve the problems associated with external logic analyzers, the described on-chip logic analyzer circuit has many limitations. First, it is a static design that cannot be changed easily. Further, during the debugging process, it may be determined that different nodes must be sampled for capture to fully determine the problem with the PLD logical design. The trigger nodes may also need to be altered to gather additional data or correct an error in the sampling process. With each subsequent change the steps of placement and routing, bit-map generation, and downloading the bit-map to the PLD must be repeated. Because these steps are quite time-consuming processes, especially on larger user logic circuit designs, multiple iterations act as a bottleneck in the debugging process.
Further, the number of user logic circuit nodes which can be captured may be restricted because storage is limited on the PLD. The limited amount of storage negatively impacts both the number of capture signals that can be simultaneously sampled and stored, as well as the rate at which the capture signals can be sampled and stored. More capture signals may be simultaneously sampled, however the sampling rate may drop due to limited block memory. Thus, the size of block memories can hinder the debugging process because efficient resolution of complex problems requires high speed sampling of many capture signals.
Embodiments of the disclosure may solve these problems as well as others.